Sr. Staff Design Engineer
Lattice Semiconductor
San Jose, CA · Posted October 30, 2026
Just laid off? Start here: a plan for the first weeks
See every open role at Lattice Semiconductor
More in California job market · Technology & Software · Engineering jobs
More roles at Lattice Semiconductor
- Vice President, Solutions R&D and PLM · San Jose, CA
- Vice President, Applications Engineering · San Jose, CA
- FPGA Architecture Engineer · San Jose, CA
- Senior Staff Integration Design Engineer · San Jose, CA
- Distinghished Solutions Architect, Edge AI · San Jose, CA
- Silicon Validation Engineer · San Jose, CA
Similar jobs
- Application Engineer II · Emcor · San Leandro, CA
- Mechanical Design Engineer (ESC) IV · Applied Materials · Santa Clara, CA
- Principal/Sr. Principal Mechanical Engineer · Northrop Grumman · Goleta, CA
- Mechanical Engineer · Top Echelon Network (recruiter member boards) · San Diego, CA
- Mechanical Engineer MTS Sr · Applied Materials · Santa Clara, CA
- Application Engineer III · Emcor · Chino, CA
Where San Jose, CA ranks
Where San Jose, CA placed in our monthly rankings, month by month. Each month stays online at its own address.
November 2026
- #1Best cities for marketing pay after cost of living$204k · of 16
- #1Best cities for aerospace and defense pay after cost of living$187k · of 19
- #2Best cities for security pay after cost of living$220k · of 10
- #3Best cities for technology pay after cost of living$205k · of 80
- #5Best cities for technology jobs1,449 openings · of 100
- #5Cities with the most jobs that do not need a four-year degree in the West Coast162 jobs · of 47
Rankings about engineering jobs
- Best cities for software and engineering jobs #1 San Francisco (3,412 openings)
- Best cities for engineering pay after cost of living #1 San Mateo ($216k)
- Most requested AI skills in engineering jobs #1 AI tools in daily work (6.1%)
- AI tools named most often in engineering jobs #1 Claude (1.7%)
- Employers with the most engineering jobs #1 Amazon (2,992 roles)
How AI is used in this kind of work
AI use among mechanical engineers is little observed so far. Measured exposure for mechanical engineers: 8% (little observed).
Share of this job’s tasks that AI is already used for at work, from real usage. It is not a forecast of job loss, and a low number means no use seen yet. Source: Anthropic Economic Index.
Skills this job asks for
Say which you have and which you want to build. We use it to match you to jobs like this one.
About the job
Lattice Overview
There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.
Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.
Job Description:
Duties:
Responsible for RTL design and verification, leveraging deep expertise in Lattice Semiconductor products and customer applications across diverse market segments.
This role involves:
Developing complex systems from concept to board-level validation using Lattice proprietary FPGA architectures and tool flows.
Building embedded systems within Lattice FPGAs, including microprocessor design and embedded software development.
Integrating IPs into FPGA software flows and supporting end-to-end system implementation.
Analyzing hardware capabilities and contributing to customer solution strategies.
Architecting Soft IPs with detailed technical specifications and coordinating development efforts.
Collaborating cross-functionally with software and applications teams to communicate requirements, resolve issues, and drive enhancements.
Specific duties include:
Architect and develop DDR Memory Controller soft IPs
Optimize soft IPs to achieve better performance (latency, size, frequency)
FPGA design and implementation using software primitives
Integration with third-party hardened PHYs
Team leadership and stakeholder management
Static Timing Analysis (STA) and constraint writing
RISC-V based system design and evaluation
Customer support and issue resolution
Quality review of third-party deliverables
Test development to validate implementation and ensure high quality
Minimum Requirements:
Bachelor’s degree in Electronics Engineering, Applied Physics or related field
8 years of experience as Design Engineer or related field
Prior experience to include:
FPGA and SoC ASIC development.
IP for FPGA and ASIC products
FPGA RTL design, logic verification, debug and timing closure
DDR protocols (e.g.: DDR3, DDR4, LPDDR4, DDR5)
High-speed interface subsystems
High-speed protocols (PCIe, Ethernet, and MIPI)
Peripheral IPs (UART, SPI, I2C, and I3C)
Hardware validation and hardware interoperability testing
Pay & Benefits
Consistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location. Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience.
For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location. The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.
Base Pay Range 0.00
In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.
Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.
Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com . You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.
As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.