Senior Staff Engineer, Physical Design
Marvell Technology
Austin, TX · Posted October 22, 2026
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Where Austin, TX ranks
Where Austin, TX placed in our monthly rankings, month by month. Each month stays online at its own address.
November 2026
- #1Best cities for professional services pay after cost of living$168k · of 25
- #1Cities with the most jobs that do not need a four-year degree in the Southwest493 jobs · of 38
- #1Best cities for pay after cost of living in the Southwest$168k · of 15
- #1Best cities for pay after cost of living in Texas$168k · of 8
- #1Best cities for software and engineering jobs in the Southwest1,931 openings · of 33
- #1Best all-round cities for mid-career professionals in the Southwest92 / 100 · of 15
Rankings about engineering jobs
- Best cities for software and engineering jobs #1 San Francisco (3,412 openings)
- Best cities for engineering pay after cost of living #1 San Mateo ($216k)
- Most requested AI skills in engineering jobs #1 AI tools in daily work (6.1%)
- AI tools named most often in engineering jobs #1 Claude (1.7%)
- Employers with the most engineering jobs #1 Amazon (2,992 roles)
Pay compared with the market
This listing does not state pay. Across 42 open senior staff engineer listings that state pay, the middle half runs $219,500 to $265,000 and the median is $240,000.
Listed pay is what employers advertise, not what people are paid.
Senior Staff Engineer salaries by state · Check your own pay
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Share of this job’s tasks that AI is already used for at work, from real usage. It is not a forecast of job loss, and a low number means no use seen yet. Source: Anthropic Economic Index.
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About the job
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Built on decades ofBuilt on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications.
What You Can Expect
You will work with both local and global team members on the physical design of complex chips as well as the methodology to enable an efficient and robust design process. This position also provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.
Key responsibilities include:
Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner.
Implement/support designs with multi-voltage designs through all aspects of implementation (place and route, static timing, physical verification) using industry standard EDA tools.
Work with RTL design teams to drive assembly and design closure.
Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes.
Write scripts in Shell, Python, and TCL to extract data and achieve productivity enhancements through automation.
What We're Looking For
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience or e quivalent professional experience in lieu of a formal degree
Expertise in full-chip & sub-hierarchy integration.
Experience integrating and taping out large designs utilizing a digital design environment.
Good understanding of RTL to GDS flows and methodology.
Good scripting skills in Perl, tcl and Python.
Good understanding of digital logic and computer architecture
Knowledge of Verilog.
Good communication skills and self-discipline contributing in a team environment.
Experience with multi-voltage and low-power design techniques is a plus.
Experience with Cadence Innovus is preferred.
Expected Base Pay Range (USD) 112,300 - 166,280, $ per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.
Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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