Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As a key CAD member of Marvell Central Engineering, you will play a leading role on developing next-generation automated design flow and add-on tools. You will have the opportunity to use your extensive design and CAD knowledge to define the whole organization's design methodology and work flow.

What You Can Expect

Develop and maintain leading-edge P&R flows addressing the needs of Marvell’s various Business Units

Power Grid implementations for various tech nodes, making sure it meets IR drop requirements

Contribute to the deployment and support of these flows

Work in collaboration with the rest of the team to ensure optimal integration inside the overall CAD platform

Come-up with innovative solutions to ever-increasing design challenges

Keep up with process and tool evolutions

Interface with EDA vendors for optimal tool usage

What We're Looking For

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 4+ years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3+ years of experience or equivalent professional experience in lieu of a formal degree

2+ years of recent experience with Cadence Innovus

Proven experience with advance nodes 5nm or below tape out. Familiar with Finfet, Dual Patterning and ULV challenges.

Experience with Power Grid implementation and IR drop analysis

Solid understanding, at least at block level but preferably at SoC level of:

Timing closure issues and ways to debug and fix them

Floorplaning and routability issues and ways to fix them

Power Grid design and validation

Various Clock synthesis schemes

SI, EM/IR, complex DRC rules

Power intent and Multiple power domains implementation.

High speed and low power implementation techniques/trade-offs.

Upstream/Downstream flow correlation

Good level of proficiency in Tcl scripting in the context of flow development

Demonstrate good analysis and problem-solving skills. Out-of-the-box thinking

Team player with good verbal and written communication skills

Preferred Qualifications:

Ability to run the following tasks is a plus:

Gate-to-gate equivalence checking

Parasitic Extraction

STA

Physical Verification (at least DRC)

Early Rail Analysis, EM/IR flow knowledge

Experience with implementation exploration methods

Experience with EDA tool benchmarks

Expected Base Pay Range (USD) 127,630 - 191,200, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.

Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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